Delivering a 15 percent improvement in test coverage for a high performance mobile SoC architecture remains my primary focus as a DFT Engineer at Intel Corporation. During the tape out of our latest 7nm processor, I identified critical scan chain bottlenecks that threatened to delay our manufacturing schedule by three weeks. By refactoring the test architecture to optimize clock distribution and scan path routing, I successfully reduced the overall test time while ensuring complete fault coverage before the silicon reached the foundry. This experience solidified my ability to navigate complex design constraints while prioritizing silicon reliability.
My technical foundation draws heavily on extensive work at NXP Semiconductors and Intel Corporation using industry standard EDA suites. I utilized Mentor Tessent to implement memory BIST on three separate chipsets, achieving a 99.8 percent diagnostic accuracy rate across all voltage corners. Additionally, I employed Synopsys DFTMAX to complete full scan insertion on a complex hierarchical design, effectively reducing transition fault defects by 12 percent. My integration of IEEE 1687 IJTAG protocols into modular systems allowed for seamless debugging during post silicon validation, ensuring that our internal design verification processes remained efficient and accurate.
Sentinel Semiconductor is leading the industry in hardware security integration, a field where my background in robust DFT architectures is directly applicable. Your commitment to high reliability in IoT device silicon perfectly aligns with my expertise in IEEE 1149.1 JTAG implementation and advanced ATPG pattern generation. I possess a deep understanding of the silicon lifecycle, from RTL design to final production testing, which will allow me to contribute immediately to your current efforts to secure chip level infrastructure. My methodical approach to design for testability ensures that performance never comes at the cost of diagnostic capability.
Securing a reliable product launch requires a balance of technical rigor and strategic planning, qualities I bring to every project. My familiarity with Cadence Modus and Synopsys Design Compiler ensures I can integrate seamlessly into your existing workflows without requiring a significant learning curve. I look forward to discussing how my experience with complex scan chains and high performance SoC validation can serve the goals of the Sentinel Semiconductor engineering team. Please contact me at your earliest convenience to arrange an interview and review my specific technical contributions further.
Best regards,
Tomasz Kowalski
