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Design Verification Engineer
Cerebras · Sunnyvale, CA
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What Cerebras asks for
From Cerebras' Design Verification Engineer ad, checked 3 Nov 2026.
SystemVerilog and UVM
At least 3 to 5 years of experience using SystemVerilog, DPI, and UVM to build testbenches and verification environments.
Verification tools and automation
Experience with simulators, waveform viewers, and build automation. You should be proficient in scripting with Python or Perl to improve verification flows.
Test development and debugging
Creating detailed tests and coverage plans, managing regressions, and debugging failures across simulation, emulation, and silicon bring-up.
Processor architecture
Knowledge of pipelined processor architecture to support high-quality silicon design.
The ad asks for 3 to 5 or more years of experience in design verification and a BS or MS in Computer Science or Electrical Engineering. Based in Sunnyvale, CA.
How the example answers the ad
SystemVerilog and UVM
“Architect and implement UVM verification environments for high-performance AI accelerators to achieve 98% functional coverage”
Architecting and implementing UVM verification environments for AI accelerators shows experience with verification methodologies and SystemVerilog-based frameworks.
Test development and debugging
“Identify and debug 15+ complex logic bugs during pre-silicon validation using waveform analysis and formal verification tools”
Identifying and debugging over 15 bugs via waveform analysis during pre-silicon validation shows the test development and debug requirement.
Verification tools and automation
“Designed automated regression frameworks with Python, cutting daily build verification time by 25%”
Creating regression frameworks using Python to reduce build time by 25 percent shows the required skills in verification tools, automation, and scripting.
Processor architecture
“Constructed scalable verification testbenches for x86 processor cores using SystemVerilog and DPI-C”
Work on x86 processor cores shows the processor architecture requirement through practical experience with specific pipelined hardware structures.
The whole example as text
Nadia Al-Rashid · Design Verification Engineer
Summary
Design Verification Engineer with 6 years of experience in high-performance processor architecture. Build UVM-based testbenches from scratch for complex AI hardware environments. Automate regression testing using Python to reduce verification cycle time by 30%. Manage coverage plans for multi-core pipelined designs from simulation through silicon bring-up.
Experience
Design Verification Engineer · NVIDIA
Santa Clara, CA · 2024 - Present
- Architect and implement UVM verification environments for high-performance AI accelerators to achieve 98% functional coverage
- Develop constrained random stimulus sequences in SystemVerilog to stress-test data paths and cache coherence protocols
- Execute simulation-to-emulation migration flows for top-level logic, reducing turnaround time by 40%
- Identify and debug 15+ complex logic bugs during pre-silicon validation using waveform analysis and formal verification tools
- Mentor two junior engineers on verification best practices and UVM class library implementation
Design Verification Engineer · AMD
Austin, TX · 2022 - 2024
- Constructed scalable verification testbenches for x86 processor cores using SystemVerilog and DPI-C
- Designed automated regression frameworks with Python, cutting daily build verification time by 25%
- Led the verification of interrupt controller modules, ensuring 100% compliance with architectural specifications
- Performed gate-level simulations to ensure timing closure and power management integrity for next-gen silicon
- Collaborated with RTL designers to resolve hardware-level issues identified during silicon bring-up
Junior Design Verification Engineer · Intel
Santa Clara, CA · 2020 - 2022
- Verified memory controller sub-systems using directed test cases and constrained random verification techniques
- Authored comprehensive verification plans and tracked coverage metrics across simulation blocks
- Automated report generation with Perl scripts to track bug resolution velocity for the verification team
- Supported post-silicon validation efforts by correlating simulation failures with lab test results
Education
Master of Science in Electrical Engineering · Stanford University
Stanford, CA · 2018 - 2020
- Maintained 3.9 GPA with a specialization in Integrated Circuit Design
- Completed thesis on formal verification methods for asynchronous logic
Bachelor of Science in Computer Engineering · Georgia Institute of Technology
Atlanta, GA · 2014 - 2018
- Graduated Summa Cum Laude
- Awarded Senior Design Excellence in Hardware Verification
Skills
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Frequently asked questions
Is the example from an employee?
No. It is an AI-written example for this ad, made to show how a resume can answer it.
What is the experience requirement for this role?
The ad lists a requirement for 3 to 5 or more years of design verification experience.
What degree is required?
The ad specifies a BS or MS in Computer Science or Electrical Engineering.
Where do I apply?
On the official Cerebras posting, through the job link on this page.
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