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Physical Design Engineer
Etched · Austin
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What Etched asks for
From Etched's Physical Design Engineer ad, checked 3 Nov 2026.
RTL to GDSII flows
Mastery of the full design methodology from RTL synthesis through to GDSII sign-off using automated tool flows.
Cadence or Synopsys tool suites
Proficiency with industry-standard EDA tools such as Innovus and Genus from Cadence, or ICC2 and Fusion Compiler from Synopsys.
Python and flow automation
Ability to program in Python or other scripting languages to automate physical design flows and improve infrastructure.
The ad asks for 5 to 10 or more years of experience in physical design. Based in Austin, with regular travel to San Jose for collaboration.
How the example answers the ad
RTL to GDSII flows
“Delivered tape-out ready GDSII within 6 months while meeting aggressive performance and area constraints.”
Reaching a tape-out ready GDSII within a six month window shows mastery of the design methodology required to produce final outputs.
Python and flow automation
“Developed Python automation scripts that reduced static timing analysis runtime by 30%.”
Creating Python scripts that cut analysis runtime by 30% is evidence of programming ability used to automate design infrastructure.
Cadence or Synopsys tool suites
“Improved power integrity sign-off accuracy by leveraging Voltus to identify and resolve IR drop hotspots.”
Using Voltus for power integrity sign-off shows proficiency with a specific tool within the Cadence suite.
The whole example as text
Sofia Martinez · Senior Physical Design Engineer
Summary
Physical design engineer with 10 years of experience in ASIC implementation for advanced process nodes. Orchestrates full RTL to GDSII workflows using industry-standard EDA tools for high-performance computing and AI hardware. Develops custom Python automation to accelerate timing closure and power optimization cycles. Delivers complex block-level designs and manages rigorous sign-off processes to meet strict PPA targets.
Experience
Senior Physical Design Engineer · NVIDIA
Santa Clara, CA · 2022 - Present
- Lead block-level physical design for AI accelerator chips using 3nm process nodes.
- Reduced total power consumption by 15% through implementation of multi-corner multi-mode optimization.
- Managed 50 million gate designs while achieving timing closure within a 4-week turnaround window.
- Developed Python automation scripts that reduced static timing analysis runtime by 30%.
Physical Design Engineer · Intel
Folsom, CA · 2019 - 2021
- Owned floorplan and power grid distribution for high-performance CPU cores at the 5nm process node.
- Achieved 98% block utilization while maintaining zero setup and hold timing violations.
- Implemented clock tree synthesis strategies that minimized clock skew by 12% across high-speed paths.
- Automated placement constraint generation using TCL scripts to accelerate design convergence by 20%.
Physical Design Engineer · Qualcomm
San Diego, CA · 2017 - 2019
- Managed comprehensive place and route workflows for mobile SoC subsystems at the 7nm node.
- Delivered tape-out ready GDSII within 6 months while meeting aggressive performance and area constraints.
- Improved power integrity sign-off accuracy by leveraging Voltus to identify and resolve IR drop hotspots.
- Executed sign-off analysis using PrimeTime and improved worst-case timing margins by 5%.
Junior Physical Design Engineer · AMD
Austin, TX · 2016 - 2017
- Supported RTL synthesis and physical design implementation for GPU peripheral subsystems.
- Executed essential physical verification tasks including DRC and LVS cleanup to ensure 100% layout compliance.
- Authored Python reporting tools to track design progress and highlight milestone bottlenecks.
- Refined floorplan layouts to optimize total wire length by 15% across critical data paths.
Education
Master of Science in Electrical Engineering · Stanford University
Stanford, CA · 2014 - 2016
- Specialized in VLSI design and computer architecture with a 3.9 GPA.
- Completed thesis on low-power clock tree synthesis techniques for sub-10nm nodes.
- Awarded Graduate Fellowship for academic excellence in integrated circuit design.
Bachelor of Science in Electrical Engineering · University of Texas at Austin
Austin, TX · 2010 - 2014
- Graduated Magna Cum Laude with honors in engineering.
- Participated in senior design capstone focused on FPGA-based signal processing.
- Served as teaching assistant for advanced digital systems design courses.
Skills
Frequently asked questions
Is the example from an employee?
No. It is an AI-written example for this ad, made to show how a resume can answer it.
Where is this role located?
The role is based in Austin. You will spend roughly two weeks per month in San Jose during the first quarter, shifting to one week per month thereafter.
Do I need experience with specific AI models?
It is not a strict requirement, but the ad notes that familiarity with modern machine learning and large language model architectures is a strength.
Where do I apply?
On the official Etched posting, through the job link on this page.
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