Your Tenstorrent resume, matched to the job ad
Drop in your resume and it opens next to this job, ready to tailor in one click.
4.8 from 167 in-app reviews
Physical Design Engineer
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Tailor your resume to this job
No account needed to start.
What Tenstorrent asks for
From Tenstorrent's Physical Design Engineer ad, checked 3 Nov 2026.
Synthesis and timing closure
Hands-on experience with synthesis, place and route, and timing closure on designs that reached tapeout.
Innovus, PrimeTime, and RedHawk
Technical expertise using industry-standard tools like Innovus, PrimeTime, and RedHawk, along with scripting in Tcl, Perl, or Python.
Advanced node and low-power design
Deep understanding of challenges on advanced process nodes and the use of low-power techniques like power gating and voltage scaling.
Power grid design and EMIR
Practical experience designing power grids and performing electromigration and IR drop analysis.
The ad asks for a BS, MS, or PhD in EE, ECE, CE, or CS. It is a hybrid role based in Austin, Santa Clara, or Fort Collins. Candidates must be eligible to access U.S. export-controlled technology.
How the example answers the ad
Innovus, PrimeTime, and RedHawk
“Performed multi-corner multi-mode timing analysis using PrimeTime, eliminating 95 percent of hold violations in the initial pass.”
Use of PrimeTime to eliminate 95 percent of hold violations is the technical expertise using industry-standard tools required for this role.
Synthesis and timing closure
“Execute full-chip synthesis and timing closure for high-speed logic blocks, maintaining setup slack within a 20ps margin across all corners.”
Maintaining setup slack within a 20ps margin across all corners for high-speed logic blocks provides the practical evidence for the synthesis and timing closure requirement.
Advanced node and low-power design
“Implemented complex power gating strategies and voltage scaling techniques to meet aggressive thermal and power budgets for server-grade silicon.”
Using power gating and voltage scaling on server-grade silicon shows the specific techniques required for advanced node and low-power design.
Power grid design and EMIR
“Design and optimize power grids for high-current density blocks, ensuring EMIR compliance by limiting IR drop to under 3 percent of Vdd.”
Limiting IR drop to under 3 percent of Vdd for high-current density blocks is the evidence for power grid design and EMIR.
The whole example as text
Michael Harris · Senior Physical Design Engineer
Summary
Physical design engineer with 6 years of experience in ASIC implementation for high-performance AI processors. Drives synthesis and timing closure for complex blocks on 5nm and 7nm process nodes using Innovus and PrimeTime. Manages power grid design and resolves critical EMIR violations with RedHawk. Automates design flows using Python and Tcl to consistently improve power, performance, and area metrics.
Experience
Senior Physical Design Engineer · NVIDIA
Santa Clara, CA · 2023 - Present
- Lead the physical implementation of a 5nm AI training chip, reducing total leakage power by 15 percent through aggressive multi-Vt cell assignment.
- Execute full-chip synthesis and timing closure for high-speed logic blocks, maintaining setup slack within a 20ps margin across all corners.
- Design and optimize power grids for high-current density blocks, ensuring EMIR compliance by limiting IR drop to under 3 percent of Vdd.
- Develop automated Tcl and Python scripts to streamline the Place and Route flow, resulting in a 20 percent reduction in block-level turnaround time.
Physical Design Engineer · AMD
Austin, TX · 2021 - 2022
- Delivered 7nm block-level designs from RTL to GDSII, meeting strict area constraints with a cell utilization efficiency of 85 percent.
- Performed multi-corner multi-mode timing analysis using PrimeTime, eliminating 95 percent of hold violations in the initial pass.
- Implemented complex power gating strategies and voltage scaling techniques to meet aggressive thermal and power budgets for server-grade silicon.
Junior Physical Design Engineer · Qualcomm
San Diego, CA · 2020 - 2020
- Participated in floorplanning and pin assignment for mixed-signal blocks, optimizing signal integrity and crosstalk margins.
- Executed standard cell library characterization and validation tasks to ensure accurate timing reports during the synthesis phase.
- Supported the tapeout process for mobile SoC components, verifying DRC and LVS compliance through multiple design cycles.
Education
MS in Electrical and Computer Engineering · University of Texas at Austin
Austin, TX · 2018 - 2020
- Graduated with 3.9 GPA
- Concentration in VLSI Design and Hardware Architecture
Skills
More Tenstorrent roles like this one
- Physical Design Engineer - STAAustin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
- Physical Design Engineer, PnRAustin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
- Physical Design Engineer, TimingAustin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Frequently asked questions
Is the example from an employee?
No. It is an AI-written example for this ad, made to show how a resume can answer it.
What experience level is Tenstorrent looking for?
The company is looking for contributors at all seniorities and will assess your level during the interview process.
What are the location requirements?
This is a hybrid role. You must be based out of the Tenstorrent offices in Austin, Texas; Santa Clara, California; or Fort Collins, Colorado.
Where do I apply?
On the official Tenstorrent posting, through the job link on this page.
What happens when I tailor my resume here?
Your resume opens in the editor next to this job. Tailor it in one click, then keep or discard the edits. You only need an account to download.