My leadership on the latest Intel Xeon project resulted in a 15 percent reduction in power consumption for high performance compute clusters by optimizing critical path timing. Leading a hardware verification team through the tapeout of a complex SoC necessitated rigorous focus on silicon reliability within strict thermal constraints. Applying this deep experience to the Senior Hardware Engineer role at Tenstorrent offers a clear opportunity to contribute to the next generation of AI hardware. Scaling high performance architectures while maintaining aggressive power efficiency targets remains the central challenge that defines my career in silicon engineering.
Driving the development of AI hardware accelerators at Intel provided the technical foundation for my expertise in RISC-V architecture and advanced RTL coding. By utilizing SystemVerilog and UVM, I reduced simulation runtime by 25 percent, which accelerated the verification cycle for our latest inference engine. During my tenure at NVIDIA, I leveraged Cadence Xcelium to debug complex cache coherency issues, resulting in a 10 percent increase in throughput for memory intensive workloads. Furthermore, my proficiency with Synopsys Design Compiler ensured consistent timing closure across multiple high speed chiplets during every major tapeout.
Tenstorrent represents the cutting edge of scalable AI silicon, and its unique approach to heterogeneous compute architectures directly aligns with my focus on building efficient, modular systems. My ability to integrate custom RISC-V cores into high performance AI fabrics fits the needs of your current development cycle perfectly. Furthermore, my hands on experience managing the transition from architectural specification to final GDSII allows me to contribute immediately to your ongoing efforts. Connecting my background in power optimized design with your proprietary AI software stack will generate significant performance gains for your customers.
My background at Intel and NVIDIA has prepared me to tackle the most demanding challenges in AI silicon design alongside your engineering team. Bringing a rigorous, methodology focused approach to the Senior Hardware Engineer position at Tenstorrent will help ensure that our next tapeout meets all performance, power, and area goals. I welcome the opportunity to discuss how my specific technical skills in RTL development and verification can support the continued growth of your AI hardware platform. Please reach out to schedule a time to talk about these technical priorities further.
Best regards,
Michael Harris