Signal Integrity Engineer Resume Example

Senior Signal Integrity Engineer · Aptiv

Troy, MI · 2022 - Present

• Led SI design and validation for multi-gigabit automotive Ethernet (1000BASE-T1) and PCIe Gen4 interfaces in ADAS ECUs, reducing signal degradation by 15% across operating temperatures.
• Performed detailed pre/post-layout simulations using Ansys SIwave and HFSS for complex 16-layer PCBs, identifying and resolving over 20 potential SI issues before prototyping, saving over $50K in re-spin costs.
• Developed automated Python scripts for post-processing VNA and TDR measurement data, improving analysis efficiency by 30% and accelerating design iterations.
• Collaborated with mechanical and thermal engineering teams to ensure optimal signal routing and impedance control in rugged automotive packaging, achieving compliance with ISO 26262.

Signal Integrity Engineer · Continental

Auburn Hills, MI · 2018 - 2021

• Conducted comprehensive SI analysis for infotainment and instrument cluster modules, including DDR4, HDMI, and USB 3.0, ensuring compliance with industry standards.
• Utilized Keysight ADS and Cadence Allegro SI to optimize PCB stack-ups and routing guidelines, improving signal quality and reducing crosstalk by up to 20% on critical data lines.
• Supported hardware teams in root cause analysis of SI and EMC related issues, implementing effective mitigation strategies that reduced field failures by 10%.
• Managed external lab testing for component characterization and system-level SI verification, coordinating activities and interpreting results for design improvements.

M.S. Electrical Engineering · University of Michigan

Ann Arbor, MI · 2015 - 2017

• Specialized in Electromagnetics and High-Speed Digital Design.
• Thesis: "Mitigation Techniques for Automotive High-Speed Data Link Reflections." Achieved GPA of 3.8/4.0.

B.S. Electrical Engineering · Purdue University

West Lafayette, IN · 2011 - 2015

• Graduated Magna Cum Laude with a GPA of 3.7/4.0.
• Awarded Dean's List honors for six consecutive semesters.

Signal Integrity Engineer · Qualcomm

San Diego, CA · 2022 - Present

• Led pre-layout and post-layout SI/PI analysis for complex SoC designs, optimizing high-speed interfaces (DDR5, PCIe Gen5) and reducing design iterations by 15%.
• Developed and implemented SI simulation methodologies for novel chip packaging technologies, improving first-pass success rate for board designs by 20%.
• Conducted root cause analysis for on-board SI failures, providing design recommendations that resolved critical issues and accelerated product qualification timelines by 10%.
• Collaborated with PCB layout and hardware design teams to define stack-up, impedance control, and power delivery network specifications, ensuring compliance with demanding performance targets.

Associate Signal Integrity Engineer · Broadcom

Austin, TX · 2020 - 2022

• Performed detailed SI analysis on DDR4 and PCIe Gen4 interfaces using Cadence Sigrity and PowerSI, identifying potential issues early in the design cycle.
• Assisted in the characterization of high-speed interconnects using VNA and TDR measurements, accurately correlating simulation models with physical prototypes, achieving 90% correlation.
• Contributed to the development of design guidelines for robust power delivery networks (PDN), leading to a 5% reduction in power noise and improved system stability.
• Supported cross-functional teams in debugging signal integrity related issues during board bring-up, reducing debugging time by an average of 1 week per project.

Hardware Design Engineer · Texas Instruments

Dallas, TX · 2018 - 2020

• Designed and validated complex mixed-signal PCBs for industrial control applications, achieving a 98% first-pass functional success rate for prototypes.
• Optimized component selection and placement to mitigate EMI/EMC issues, resulting in a 10% reduction in design costs related to shielding and filtering.
• Performed initial pre-layout signal integrity checks and impedance matching for high-speed traces (e.g., SPI, LVDS), preventing major redesigns and saving approximately $15,000 per board spin.
• Developed automated test scripts using Python for board-level validation, improving test efficiency by 25% and reducing manual testing efforts.

Master of Science in Electrical and Computer Engineering · University of Texas at Austin

Austin, TX · 2020 - 2022

• Specialization in Electromagnetics and High-Speed Digital Design
• Relevant Coursework: Advanced Signal Integrity, RF and Microwave Engineering, Analog Integrated Circuit Design
• GPA: 3.9/4.0

Bachelor of Science in Electrical Engineering · Georgia Institute of Technology

Atlanta, GA · 2014 - 2018

• Concentration in Digital Systems and Microelectronics
• Honors: Magna Cum Laude
• Dean's List: 6 semesters